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Product Description:
Silicon on insulator (SOI) technology refers to a structure of a thin silicon layer on an insulator, such as silicon dioxide. This structure separates the active silicon layer from the bulk substrate, the handle wafer, to improve device performance for CMOS devices and more flexible integration schemes for electronic, MEMS devoices.
Specification:
| Processing Method |
SIMOX, BONDING, SIMBOND |
| Diameter |
3, 4, 5, 6, 8, 12 Inches
|
| Front side Finish |
Polished
|
| Backside Finish |
Ground/Polished or Others
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| Edge Exclusion |
2~5mm or less
|
Handle Wafer
|
| Crystal & Growth Method |
Silicon & CZ or FZ
|
| Substrate Thickness |
100μm / 300μm / 400μm / 500μm / 625μm ~ Up
|
| Orientation |
<100>, <110>, <111> ± 0.5 degree
|
| Dopant |
N(Phos., As, Sb) / P(Boron)
|
| Conductivity type |
N / P
|
| Resistivity |
0.01~10,000 ohm•cm or Upon request
|
| Primary Flat Length |
Semi-std
|
BOX (Buried Oxide Layer)
|
| Buried Thickness |
100 nm to 10μm typical
|
| Growth Type |
Thermal Oxide
|
| Formed on |
Handle Wafer
|
Device Layer (Multilayer Available)
|
| Thickness of Top Layer |
≥ 20 nm
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| Crystal Growth Method |
CZ or FZ
|
| Orientation |
<100>,<110>,<111> ± 0.5 degree
|
| Dopant |
N(Phos., As, Sb)/P(Boron)
|
| Conductivity type |
N / P
|
| Resistivity |
0.001~100 ohm•cm or Upon request
|
| Primary Flat Length |
Semi-std
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| Light Point Defect (LPD) |
Optional per customer request
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| Crack |
NONE
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| Haze |
NONE
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| Voids (> 0.5mm² in size) |
NONE
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